Multilayer printed wiring board

ABSTRACT

A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer  34 P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit  58  on an interlayer resin insulating layer  50  is formed to have a thickness of 15 μm. By making the conductor layer  34 P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer  34  as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

TECHNICAL FIELD

This invention relates to a multilayer printed wiring board and providesa technique related to a multilayer printed wiring board capable ofhaving improved electric characteristics and reliability without causingmalfunction, error or the like even if a high frequency IC chip,particularly an IC chip in a high frequency range of 3 GHz or higher ismounted thereon.

BACKGROUND ART

In forming a buildup type multilayer printed wiring board constitutingan IC chip package, interlayer insulating resin is formed on one of oreach of the surfaces of a core substrate having through holes formedtherein and via holes for interlayer conduction are opened by a laser orphoto etching, whereby an interlayer resin insulating layer is therebyformed. A conductor layer is formed on the via holes by plating or thelike and etching and the like are performed to form a pattern, thuscreating a conductor circuit. Further, by repeatedly forming theinterlayer insulating layer and the conductor layer, the buildupmultilayer printed wiring board is obtained. By forming solder bumps andexternal terminals (PGA/BGA's or the like) on the front layer of theboard at need, the board becomes a substrate capable of mounting an ICchip thereon or a package substrate. The IC chip is C4 (flip-chip)mounted, whereby the IC chip is electrically connected to the substrate.

As prior art of the buildup type multilayer printed wiring board, thereare known JP1994-260756A and JP1994-275959A. In both of thepublications, a land is formed on a core substrate having through holesfilled with resin filler, interlayer insulating layers having via holesformed therein are provided on the both surfaces of the substrate,respectively, a conductor layer is formed by an additive method and theconductor layer is connected to the land, thereby obtaining a highdensity multilayer wiring board having fine wirings formed thereon.

However, as the frequency of an IC chip is higher, the frequency ofoccurrence of malfunction or error becomes higher. Particularly if thefrequency of the IC chip exceeds 3 GHz, the frequency of occurrence ofmalfunction or error considerably increases. If the frequency exceeds 5GHz, the IC chip often turns inoperative. Due to this, a computerincluding the IC chip as a CPU cannot perform operations that thecomputer should do, i.e., cannot perform desired functions andoperations such as the recognition of an image, the changeover of aswitch and the transmission of data to the outside of the computer.

If the substrate for an IC chip of this type is to be subjected to anon-destructive test and to be dissembled, no problems such asshort-circuit or opens do not occur to the substrate itself and if theIC chip having a low frequency (particularly less than 1 GHz) is mountedon the substrate, then no malfunction or error occurs to the IC chip.

The present invention has been achieved to solve the above-stateddisadvantages and the object of the present invention is to provide amultilayer printed wiring board capable of being constituted as aprinted board or a package substrate free of malfunction or error evenwith an IC chip in a high frequency range, particularly, with afrequency exceeding 3 GHz.

DISCLOSURE OF THE INVENTION

The inventors of the present invention achieved the invention mainlyconstituted as shown in the following contents as a result of devotedstudies to the realization of the above object.

According to the present invention, a multilayer printed wiring boardhaving an interlayer insulating layer and a conductor layer formed on acore substrate, the conductor layer being electrically connected througha via hole, is characterized in that

-   -   a thickness of the conductor layer on the core substrate is        larger than a thickness of the conductor layer on the interlayer        insulating layer.

The first advantage of the invention is that by making the conductorlayer as the power supply layer of the core substrate thick, it ispossible to intensify the strength of the core substrate and that evenif the core substrate itself is made thin, it is possible for thesubstrate itself to relax warps and generated stresses.

The second advantage of the invention is that by making the conductorlayers thick, it is possible to increase the volumes of the conductorsthemselves. By increasing the volumes, it is possible to decrease theresistances of the conductors. Due to this, the electrical transmissionof the signal line or the like is not hampered. Accordingly, the loss ofthe signal transmitted or the like does not occur. This advantage isexhibited by making only the substrate which becomes the core thick.

The third advantage of the invention is that by employing the conductorlayer as the power supply layer, it is possible to improve thecapability of supplying power to the IC chip. In addition, by employingthe conductor layer as the earth layer, it is possible to decrease thenoise superposed on the signal and power to the IC chip. This is becausethe decreased resistances of the conductors as described as the secondadvantage can prevent the supply of power from being hampered. Due tothis, if the IC chip is mounted on the multilayer printed wiring board,it is possible to decrease a loop inductance from the IC chip—thesubstrate—the power supply. Accordingly, power shortage in an initialoperation is decreased to make it difficult to cause power shortage.Even if the IC chip in a higher frequency range is mounted on themultilayer printed wiring board, malfunction, error or the like does notoccur in the initial operation.

Further, even if the power is supplied to the IC chip via the ICchip—the substrate—capacitors or the power supply layer—power, the sameadvantage can be exhibited. The loop inductance can be decreased. Forthis reason, no loss occurs to the supply of power to the capacitors ordielectric layers. In the first place, the IC chip performs complexarithmetic processings and operations while instantaneously consumingpower. By supplying power from the power supply layer to the IC chip, itis possible to supply the power without the need to mount manycapacitors even if the IC chip in a high frequency range is mounted andpower shortage (a state of the occurrence of voltage drop) occurs in theinitial operation. Power shortage (voltage drop) in the initialoperation occurs so as to employ the IC chip in the high frequencyrange. If the conventional IC chip is used, the necessary power issufficiently supplied by the capacity of the capacitors or dielectriclayers.

Particularly if the thickness of the conductor layer serving as thepower supply layer of the core substrate is larger than the thickness ofthe conductor layer on the interlayer insulating layer on each surfaceor both surfaces of the core substrate, the three advantages statedabove can be maximized. The conductor layer on the interlayer insulatinglayer mainly means herein a conductor layer formed by forming via holeswhich are non-through holes for interlayer connection in an interlayerresin insulating layer made of resin the core material of which is notimpregnated and conducting plating and sputtering. As long as theconductor layer has via holes formed therein, but not limited thereto,the conductor layer can be used as the conductor layer on the interlayerinsulating layer.

The power supply layer of the core substrate may be arranged on thesurface layer or inner layer of the substrate or on each of the surfacelayer and the inner layer. If the power supply layer is formed on theinner layer, a plurality of layers of two or more may be arranged.Basically, as long as the power supply layer of the core substrate isthicker than the conductor layer of the interlayer insulating layer, theadvantage of the power supply layer can be exhibited.

It is, however, preferable to form the power supply layer on the innerlayer. If it is formed on the inner layer, the power supply layer isarranged between the IC chip and the external terminals or capacitors.Due to this, the distances between the IC chip and the externalterminals or capacitors are uniform, which decreases hampering factorsand can suppress power shortage.

Further, according to the present invention, a multilayer printed wiringboard having an interlayer insulating layer and a conductor layer formedon a core substrate, the conductor layer being electrically connectedthrough a via hole, is characterized in that

-   -   if a thickness of the conductor layer on said core substrate is        α1 and a thickness of the conductor layer on the interlayer        insulating layer is α2, α1 and α2 satisfy α2<α1≦40α2.

At α1<α2, the advantage against the power shortage is not exhibited atall. That is, it is not clear that the voltage drop which occurs in theinitial operation is suppressed.

A case in which al exceeds 40α2 (α1>40α2) has been also considered.However, the electrical characteristics of al are basically equal tothose of 40α2. That is, it is understood that 40α2 is a critical pointof the advantage of the present application. Even if α1 is larger than40α, the improvement of the electrical advantage cannot be expected.Nevertheless, if α1 exceeds 40α and the conductor layer is formed on thesurface layer of the core substrate, it is difficult to form lands orthe like for the connection of the conductor layer to the coresubstrate. If the further upper interlayer insulating layer is formed,irregularities grow and waviness sometimes occurs to the interlayerinsulating layers and impedances cannot be matched. However, that range(α1>40α2) does not often cause any problem depending on the materials.

It is more preferable that al satisfies 1.2α2≦α1≦40α2. It is confirmedthat the malfunction, error or the like of the IC chip due to the powershortage (voltage drop) does not occur.

The core substrate means herein a resin substrate the core material ofwhich, such as glass epoxy resin, is impregnated, a ceramic substrate, ametal substrate, a composite core substrate using a combination ofresin, ceramic and metal, a substrate having a (power supply) conductorlayer provided on the inner layer of the substrate, a multilayer coresubstrate having three or more conductor layers formed thereon, or thelike.

To make the conductor of the power supply layer thick, the conductorlayer may be formed on the substrate buried with metal by an ordinarymethod in relation to the printed wiring board for forming the conductorlayer by plating, sputtering or the like.

If the substrate is the multilayer core substrate, the sum of thethickness of the conductor layer on the surface layer of the coresubstrate and that of the conductor layer on the inner layer of the coresubstrate is equal to the thickness of the conductor layers of the core.In this case, the multilayer wiring board is employed if the conductorlayer on the surface layer is electrically connected to the conductorlayer on the inner layer and the electrical connection thereof isestablished in two or more portions. That is, even if the number oflayers increases, the thickness of the conductor layers of the coresubstrate is to be increased but the advantage remains the same.Further, if the area of a conductor layer is almost equal to that of apad or a land, the thickness of the conductor layer is not considered tobe added. It is preferable that the conductor layer is the power supplylayer or the earth layer.

In this case, the core substrate may comprise three layers (surfacelayers+inner layer). A multilayer core substrate comprising three ormore may be used.

If necessary, such components as capacitors, dielectric layers orresistances may be buried in the inner layer of the core substrate andan electric component containing core substrate thus formed may be used.

Further, if the conductor layer on the inner layer of the core substrateis made thick, it is preferable to arrange the conductor layers rightunder the IC chip. By arranging the conductor layers right under the ICchip, it is possible to minimize the distance between the IC chip andthe power supply layer and to thereby further decrease the loopinductance. Accordingly, power is supplied more efficiently and thepower shortage problem is solved. At this time, it is preferable that ifthe thickness of the conductor layer on the core substrate is al and thethickness of the conductor layer on the interlayer insulating layer isα2, α1 and α2 satisfy α2<α1≦40α2.

The core substrate according to the present invention is defined asfollows. The core substrate is constituted so that the substrate is madeof a hard base material such as resin the core material of which isimpregnated, photo-via holes or laser via holes are formed therein usinginsulating resin layers each of which does not include a core materialor the like, conductor layers are formed, and interlayer electricalconnection is established. The thickness of the core substrate isrelatively larger than that of each resin insulating layer. Basically,the conductor layer mainly used as a power supply layer is formed andother signal lines or the like are formed only for the connectionbetween the front and rear surfaces of the substrate.

In case of a multilayer printed wiring board having a plurality oflayers made of materials equal in thickness and built up, the layerhaving the power supply layer as the conductor layer on the printedboard or the substrate is defined as the core substrate.

It is also preferable that the multilayer core substrate is such that arelatively thick conductor layer is provided on the inner layer, arelatively thin conductor layer is provided on the surface layer andthat the conductor layer on the inner layer is a conductor layer mainlyfor a power supply layer or an earth. (Relatively thick and relativelythin mean herein that if the thicknesses of all the conductor layers arecompared and there are a relatively thick layer and a relatively thinlayer, then the inner layer is relatively thick to the other conductorlayers and the surface layer is relatively thin.)

Namely, by arranging the thick conductor layer on the inner layer side,it is possible to form the resin layer to cover the conductor layer onthe inner layer and ensure the flatness of the core even if thethickness of the thick conductor layer is arbitrarily changed. Due tothis, waviness does not occur to the conductor layer of the interlayerinsulating layer. Even if the thin conductor layer is arranged on thesurface layer of the multilayer core substrate, it is possible to securea sufficient thickness of the conductor layers as those of the core byadding together the thicknesses of the thin conductor layer and theconductor layer on the inner layer. By employing the conductor layersfor power supply layers or earth layers, it is possible to improve theelectrical characteristics of the multilayer printed wiring board.

The thickness of the conductor layer on the inner layer of the coresubstrate is made larger than the thickness of the conductor layer onthe interlayer insulating layer. By doing so, even if the conductorlayer is arranged on the surface of the multilayer core substrate, it ispossible to secure the sufficient thickness of the conductor layers ofthe core by adding together the thicknesses of the conductor layer onthe surface of the substrate and the thick conductor layer on the innerlayer. Namely, even if a large capacity of power is supplied, the ICchip can be actuated without causing any problems, so that nomalfunction or operational defect occurs to the IC chip. At this time,it is preferable that if the thickness of the conductor layer on thecore substrate is al and the thickness of the conductor layer on theinterlayer insulating layer is α2, α1 and α2 satisfy α2<α1≦40α2.

In case of a multilayer core substrate, it is preferable that theconductor layer on the inner layer is made relatively thick and used asa power supply layer, and that the conductor layers on the surface layerare formed to put the conductor layer on the inner layer therebetweenand used as signal lines. With this structure, it is possible tointensify power as described above.

Furthermore, by arranging the signal line between the conductor layersin the core substrate, it is possible to form a micro-strip structure.Due to this, it is possible to decrease inductance and to matchimpedances to one another. It is thereby possible to stabilize theelectric characteristics of the multilayer printed wiring board. It isfurther preferable that the conductor layer on the surface layer isrelatively thin. The through hole pitch of the core substrate may be notmore than 600 μm.

It is preferable that the multilayer core substrate is constituted sothat the conductor layer on the inner layer is formed on the eachsurface of the metallic plate electrically connected to the conductorlayer through a resin layer and that the conductor layer on the surfaceis formed outside of the inner layer conductor layer through a resinlayer. By arranging the electrically insulated metallic plate in thecentral portion, it is possible to secure sufficient mechanicalstrength. Further, by forming the inner layer conductor layer on eachsurface of the metallic plate through the resin layer and forming thesurface conductor layer outside of the inner layer conductor layerthrough the resin layer, it is possible to impart symmetry to the bothsurfaces of the metallic plate and to prevent the occurrence of warps,waviness and the like in a heat cycle and the like.

In FIG. 24, the vertical axis indicates voltage supplied to the IC chipand the horizontal axis indicates passage of time. In FIG. 24, printedwiring boards without capacitors for the power supply of IC chip withhigh frequency of 1 GHz or higher are used as models. A curve A showsthe change of the voltage to an IC chip with 1 GHz with the passage oftime, and a curve B shows the change of the voltage to an IC chip with 3GHz with the passage of time. According to each voltage change withtime, when the IC chip starts to be actuated, a large quantity of poweris instantaneously required. If the supply of power is insufficient,voltage drops (at point X or X′). Thereafter, the power to be suppliedis gradually added, so that the voltage drop is eliminated. However, ifthe voltage drops, malfunction or error tends to occur to the IC chip.That is, a defect caused by the insufficient function or actuation ofthe IC chip due to lack of the supply of power occurs. This powershortage (voltage drop) grows as the frequency of the IC chip is higher.Due to this, it takes time to solve the voltage drop problem and a timelag occurs in allowing the IC to perform a desired function or actuatingthe IC.

To compensate for the power shortage (voltage drop), the IC chip isconnected to an external capacitor and the power accumulated in thecapacitor is discharged, whereby the power shortage or voltage dropproblem can be solved.

In FIG. 25, printed boards with capacitors are used as models. A curve Cshows the change of the voltage to the IC chip with 1 GHz with thepassage of time if a small capacity of a capacitor is mounted on theboard. Compared with the curve A which shows a case where the capacitoris not mounted, the degree of the voltage drop of the curve C is low.Further, a curve D shows the change of the voltage to the IC with thepassage of time similarly to the curve C if a capacitor larger incapacity than the capacitor mounted in case of the curve C. Comparedwith the curve C, the degree of the voltage drop of the curve D islower. Thus, in case of the curve D, it is possible to function andactuate a desired chip in short time. However, as shown in FIG. 24, ifthe frequency of the IC chip is higher, a larger capacity of thecapacitor is required. As a result, the region on which the capacitor ismounted needs to be established. Therefore it is difficult to secure thevoltage, it is impossible to improve the operation and function of theIC chip and it is difficult to improve the density of the IC chip.

FIG. 26 is a graph if the thickness of the conductor layer of the coresubstrate and that of the conductor layer as the power supply is al andthat of the conductor layer on the interlayer insulating layer is α2. InFIG. 26, a curve C shows the change of the voltage with the passage oftime if a small capacity of a capacitor is mounted on an IC chip with 1GHz and α1=α2. A curve F shows the change of the voltage with thepassage of time if a small capacity of a capacitor is mounted on the ICchip with 1 GHz and α1=1.5α2. A curve E shows the change of the voltagewith the passage of time if a small capacity of a capacitor is mountedon the IC chip with 1 GHz and α1=2.0α2. As the conductor layer of thecore is thicker, the power shortage or voltage drop becomes lower. Dueto this, it may be said that the malfunction of the IC chip less occurs.By making the conductor layer of the core substrate and the conductorlayer as the power supply layer thick, the volumes of the conductorlayers increase. If the volumes increase, the conductor resistancesdecrease, so that the loss of the power to be transmitted to the voltageor current is eliminated. As a result, power is supplied while thetransmission loss between the IC chip and the power supply is lowered,no malfunction or error occurs to the IC chip. This is mainly thanks tothe thickness of the conductor layer as the power supply layer; bymaking the conductor layer as the power supply layer of the coresubstrate thicker than that on the other interlayer insulating layer,the advantage can be exhibited.

Furthermore, it is discovered that the advantage attained if theconductor formed on the surface layer on one surface or each surface ofthe core substrate and the conductor layer as the power supply layer aremade thick can be also exhibited if the multilayer core substrate whichcomprises three or more layers is used and in which the conductor layeris formed on the inner layer or the conductor layer as the power supplylayer is formed on the inner layer. Namely, the advantage of decreasingpower shortage or voltage drop can be exhibited. If the multilayer coresubstrate is employed, this advantage is exhibited when the sum of thethicknesses of all the conductor layers is larger than the thicknessesof the conductor layers on the interlayer insulating layers even if thethicknesses of the all the conductor layers and conductor layers for thepower supply layers are smaller than the thicknesses of the conductorlayers on the interlayer insulating layers or even if the thicknesses ofthe all the conductor layers and conductor layers for the power supplylayers are equal to or smaller than the thicknesses of the conductorlayers on the interlayer insulating layers. In this case, there is nodifference in area among the conductor layers. In other words, thisadvantage is exhibited when all the conductor layers are equal in area.For example, if two conductor layers are provided, the one is a solidlayer having a large area and the other has an area as small as a viahole or the land thereof, then the advantage of the one conductor layeris canceled by the other conductor layer.

Furthermore, even if the core substrate includes electronic componentssuch as capacitors, dielectric layers or resistances, this advantage isconspicuously exhibited. By including the electronic components in thesubstrate, it is possible to shorten the distance between the IC chipand each capacitor or dielectric layer. It is, therefore, possible todecrease the loop inductance. It is possible to decrease the powershortage or voltage drop. In case of the core substrate includingtherein capacitors or dielectric layers, for example, by making thethicknesses of the conductor layers of the core substrate and theconductor layers as the power supply layer larger than the conductorlayers on the interlayer insulating layers, it is possible to decreasethe resistances of the conductors of both the main power supply and thepower of the included capacitors or dielectric layer, thereby making itpossible to decrease transmission loss and to further exhibit theadvantage of the substrate including therein capacitors.

As the core substrate, the resin substrate is employed. However, it isdiscovered that the ceramic or metal core substrate exhibits the sameadvantage. As the material of the conductor layer, copper is employed.Even if the other metals are employed, it is not confirmed that theadvantage is cancelled and malfunction or error occurs to the IC chip.It, therefore, appears that the advantage is not influenced by thedifference in the material of the core substrate or the difference inthe material of the conductor layers. It is more preferable that theconductor layers of the core substrate and those of the interlayerinsulating layer are made of the same metal. This is because theadvantages of the present application can be exhibited since there is nodifference in such characteristics as electrical characteristics and thecoefficient of thermal expansion and physical properties between theconductor layers of the core substrate and those of the interlayerinsulating layers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a step diagram showing a method for manufacturing a multilayerprinted wiring board according to Embodiment 1 of the present invention.

FIG. 2 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 1.

FIG. 3 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 1.

FIG. 4 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 1.

FIG. 5 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 1.

FIG. 6 is a cross-sectional view of the multilayer printed wiring boardaccording to Embodiment 1.

FIG. 7 is a cross-sectional view showing a state in which an IC chip ismounted on the multilayer printed wiring board according to Embodiment1.

FIG. 8 is a cross-sectional view of the multilayer printed wiring boardaccording to Embodiment 3.

FIG. 9 is a cross-sectional view showing a state in which an IC chip ismounted on the multilayer printed wiring board according to Embodiment3.

FIG. 10 is a cross-sectional view of a multilayer printed wiring boardaccording to Embodiment 4.

FIG. 11 is a cross-sectional view showing a state in which an IC chip ismounted on the multilayer printed wiring board according to Embodiment4.

FIG. 12 is a step diagram showing method for manufacturing a multilayerprinted wiring board according to Embodiment 5 of the present invention.

FIG. 13 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 5.

FIG. 14 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 5.

FIG. 15 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 5.

FIG. 16 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 5.

FIG. 17 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 5.

FIG. 18 is a step diagram showing the method for manufacturing themultilayer printed wiring board according to Embodiment 5.

FIG. 19 is a cross-sectional view of the multilayer printed wiring boardaccording to Embodiment 5.

FIG. 20 is a cross-sectional view showing a state in which an IC chip ismounted on the multilayer printed wiring board according to Embodiment5.

FIG. 21 is a cross-sectional view showing a state in which an IC chip ismounted on a multilayer printed wiring board according to a modificationof Embodiment 5.

FIG. 22 is a cross-sectional view of the multilayer printed wiring boardaccording to Embodiment 6.

FIG. 23 is a cross-sectional view showing a state in which an IC chip ismounted on a multilayer printed wiring board according to a modificationof Embodiment 6.

FIG. 24 is a graph showing voltage change during the operation of the ICchip.

FIG. 25 is a graph showing voltage change during the operation of the ICchip.

FIG. 26 is a graph showing voltage change during the operation of the ICchip.

FIG. 27 is a table showing the test results of Embodiments and acomparison example.

FIG. 28 is a table showing the test results of Embodiments and acomparison example.

FIG. 29 is a graph showing the result of simulating a maximum voltagedrop quantity (V) for (a ratio of thickness of power supply layer ofcore/thickness of interlayer insulating layer)

BEST MODES FOR CARRYING OUT THE INVENTION Embodiment 1 Glass Epoxy ResinSubstrate

The configuration of a multilayer printed wiring board 10 according toEmbodiment 1 of the present invention will first be described withreference to FIGS. 1 to 7. FIG. 6 shows the cross section of themultilayer printed wiring board 10 and FIG. 7 shows a state in which anIC chip 90 is attached to the multilayer printed wiring board 10 shownin FIG. 6 and in which the board 10 is mounted on a daughter board 94.As shown in FIG. 6, the multilayer printed wiring board 10 has aconductor circuit 34 and a conductor layer 34P formed on the frontsurface of a core substrate 30, and a conductor circuit 34 and aconductor layer 34E formed on the rear surface of the core substrate 30.The upper conductor layer 34P is formed as a power supply plane layerwhile the lower conductor layer 34E is formed as an earth plane layer.The front and rear surfaces of the core substrate 30 are connected toeach other via through holes 36. In addition, an interlayer resininsulating layer 50 on which via holes 60 and conductor circuits 58 areformed and an interlayer resin insulating layer 150 on which via holes160 and conductor circuits 158 are formed are provided on each of theconductor layers 34P and 34E. Solder resist layers 70 are formed onupper layers of the via holes 160 and the conductor circuits 158, andbumps 76U and 76D are formed on the via holes 160 and the conductorcircuits 158 through the opening portions 71 of the solder resist layers70, respectively.

As shown in FIG. 7, solder bumps 76U on the upper surface of themultilayer printed wiring board 10 are connected to lands 92 of the ICchip 90. Further, chip capacitors 98 are mounted on the board 10. Solderbumps 76D on the lower surface thereof are connected to lands 96 of thedaughter board 94.

The conductor, layers 34P and 34E on the core substrate 30 are eachformed to have a thickness of 1 to 250 μm, and the conductor circuits 58on the interlayer resin insulating layers 50 and the conductor circuits158 on the interlayer resin insulating layers 150 are each formed tohave a thickness of 5 to 25 μm (preferably 10 to 20 μm).

On the multilayer printed wiring board according to Embodiment 1, thepower supply layer (conductor layer) 34P and the conductor layer 34E ofthe core substrate 30 are made thick, thereby intensifying the strengthof the core substrate, for which reason it is possible for the coresubstrate itself to relax warps and generated stresses even if the coresubstrate is made thin.

Furthermore, it is possible to increase the volumes of the conductorsthemselves by making the conductor layers 34P and 34E thick and todecrease the resistances of the conductors by increasing the volumesthereof.

In addition, by employing the conductor layer 34P as a power supplylayer, it is possible to improve the capability of supplying power tothe IC chip 90. Due to this, when the IC chip is mounted on themultilayer printed wiring board, it is possible to decrease a loopinductance of the IC chip—the substrate—the power supply. Accordingly,power shortage in an initial operation is decreased to make it difficultto cause power shortage. Therefore, even if the IC chip in a higherfrequency range is mounted on the multilayer printed wiring board,malfunction, error or the like does not occur in the initial operation.Besides, by employing the conductor layer 34E as an earth layer, noisedoes not superpose on the signal of the IC chip and the supply of powerto the IC chip, thus making it possible to prevent malfunction or error.

A method for manufacturing the multilayer printed wiring board 10described above with reference to FIG. 6 will next be described withreference to FIGS. 1 to 5.

Embodiment 1-1

A. Manufacturing of Resin Film of Interlayer Resin Insulating Layer

29 parts by weight of bisphenol A type epoxy resin (epoxy equivalentweight of 455, Epicoat 1001 manufactured by Yuka Shell Epoxy), 39 partsby weight of cresol novolac type epoxy resin (epoxy equivalent weight of215, EpiclonN-673 manufactured by Dainippon Ink and Chemicals) and 30parts by weight of phenol novolac resin including a triazine structure(phenol hydroxyl group equivalent weight of 120, PhenoliteKA-7052manufactured by Dainippon Ink and Chemicals) are heated and molten whilebeing agitated with 20 parts by weight of ethyl diglycol acetate and 20parts by weight of solvent naphtha, and 15 parts by weight of terminallyepoxidized polybutadiene rubber (DenalexR-45EPT manufactured by NagaseChemicals Ltd.) and 1.5 parts by weight of crushed product of2-phenyl-4,5-bis(hydroxymethyl)imidazole, 2.5 parts by weight ofpulverized silica and 0.5 parts by weight of silicon-based defoamingagent are added thereto, thereby preparing an epoxy resin composition.

The obtained epoxy resin composition is coated on a PET film having athickness of 38 μm so as to have a thickness of 50 μm after being driedby a roll coater and dried for 10 minutes at 80 to 120° C., therebymanufacturing a resin film for an interlayer resin insulating layer.

B. Preparation of Resin Filler

100 parts by weight of bisphenol F type epoxy monomer (manufactured byYuka Shell, molecular weight: 310, YL983U), 170 parts by weight of SiO₂spheroidal particles having a silane coupling agent coated on surfacesthereof, a mean particle size of 1.6 μm, and a largest particle size ofnot more than 15 μm (manufactured by ADTEC Corporation, CRS 1101-CE) and1.5 parts by weight of leveling agent (manufactured by Sannopuko KK,PelenolS4) are input in a container and agitated and mixed therein,thereby preparing resin filler having a viscosity of 44 to 49 Pa.s at23±1° C. As hardening agent, 6.5 parts by weight of imidazole hardeningagent (manufactured by Shikoku Chemicals, 2E4MZ-CN) is used. As theresin filler, thermosetting resin such as the other epoxy resin (e.g.,bisphenol A type, novolac type or the like), polyimide resin or phenolresin may be used.

C. Manufacturing of Multilayer Printed Wiring Board

(1) A copper-clad laminate 30A having copper foils 32 of 5 to 250 μmlaminated on the both surfaces of an insulative substrate 30 made ofglass epoxy resin having a thickness of 0.2-0.8 mm or BT(Bismaleimide-Triazine) resin, respectively, is used as a startingmaterial (FIG. 1(A)). First, this copper-clad laminate 30A is drilled,subjected to an electroless plating treatment and an electroplatingtreatment, and etched into a pattern to thereby form conductor circuits34, conductor layers 34P and 34E and through holes 36 on the bothsurfaces of the substrate, respectively (FIG. 1(B)).

(2) After washing and drying the substrate 30 having the through holes36 and the lower layer conductor circuits 34 formed thereon, anoxidization treatment using an aqueous solution containing NaOH (10g/l), NaClO2 (40 g/l) and Na3PO4 (6 g/l) as a blackening bath (anoxidation bath) and a reduction treatment using an aqueous solutioncontaining NaOH (10 g/l) and NaBH4 (6 g/l) as a reduction bath areconducted to the substrate 30, thereby respectively forming roughenedsurfaces 36 a in the through holes 36 and roughened surfaces 34α on theentire surfaces of the conductor circuits 34 and the conductor layers34P and 34E (FIG. 1(C)).

(3) After preparing the resin filler described in B above, within 24hours of preparation, according to the following method, layers of theresin filler 40 are formed in the through holes 36 and on the conductorcircuit unformed portions of the substrate, respectively (FIG. 1(D)).

Namely, a resin filling mask having openings in portions correspondingto the through holes and the conductor circuit unformed portions is puton the substrate, and the resin filler 40 is filled into the throughholes, depressed lower layer conductor circuit unformed portions and theouter edges of the lower layer conductor circuits with a squeegee andthen dried at 100° C. for 20 minutes.

(4) One of the surfaces of the substrate which has been subjected to thetreatment of (3) is polished by belt sander polishing using #600 beltabrasive paper (manufactured by Sankyo Rikagaku Co.) so as not to leavethe resin filler 40 on the outer edges of the conductor layers 34P and34E and those of the lands of the through holes 36, and the entiresurfaces of the conductor layers 34P and 34E (including the landsurfaces of the through holes) are then buffed to remove scratchescaused by the belt sander polishing. A series of these polishingtreatments are similarly conducted to the other surface of thesubstrate. The resin filler 40 is then heated at 100° C. for 1 hour andat 150° C. for 1 hour and hardened (FIG. 2(A)).

As a result, a substrate in which the surface layer portions of theresin fillers 40 formed in the through holes 36 and on the conductorcircuit unformed portions and the surfaces of the conductor layers 34Pand 34E are flattened, the resin fillers 40 are fixedly attached to theside surfaces of the conductor layers 34P and 34E through the roughenedsurfaces and the inner wall surfaces of the through holes 36 are fixedlyattached to the resin fillers through the roughened surfaces, isobtained. That is to say, through the steps, the surfaces of the resinfillers become almost flush with those of the lower layer conductorcircuits.

The conductor layers of the core substrate are formed to have athickness of 1 to 250 μm and the conductor layer serving as the powersupply layer and formed on the core substrate is formed to have athickness of 1 to 250 μm. Here in Embodiment 1-1, the conductor layersof the core substrate are formed to have a thickness of 30 μm and theconductor layer serving as the power supply layers and formed on thecore substrate is formed to have a thickness of 30 μm using the copperfoils of 40 μm. However, the thicknesses of the conductor layers mayexceed the above thickness range.

(5) After washing and acid-degreasing the substrate, soft etching isconducted to the substrate and etchant is sprayed onto the both surfacesthereof to etch the surfaces of the conductor circuits 34, the conductorlayers 34P and 34E and the land surfaces of the through holes 36,thereby forming roughened surfaces 36, on the entire surfaces of therespective conductor circuits (see FIG. 2(B)). As the etchant, etchant(manufactured by Mech Corporation, Mech-Etch Bond) comprising 10 partsby weight of an imidazole copper (II) complex, 7.3 parts by weight ofglycolic acid and 5 parts by weight of potassium chloride is used.

(6) Interlayer resin insulating layer resin films 50γ slightly largerthan the substrate manufactured in A are put on the both surfaces of thesubstrate, respectively, temporarily press-fitted under conditions ofpressure of 0.45 MPa, a temperature of 80° C. and press-fit time of 10seconds and cut, and then bonded using a vacuum laminator by thefollowing method, thereby forming interlayer resin insulating layers(FIG. 2(C)). Namely, the interlayer resin insulating layer resin filmsare actually press-fitted onto the substrate under conditions of vacuumof 67 Pa, pressure of 0.47 MPa, a temperature of 85° C. and press-fittime of 60 seconds, and then thermally hardened at 170° C. for 40minutes.

(7) Next, through a mask having pass-through holes having a thickness of1.2 mm formed therein, openings 50 a for via holes are formed to have adiameter between 60 to 100 μm in the interlayer resin insulating layers2 by a CO2 gas laser at a wavelength of 10.4 μm under conditions of abeam diameter of 4.0 mm, a top hat mode, a pulse width of 8.1microseconds, the pass-through hole diameter of the mask of 1.0 mm andone shot (FIG. 2(D)). In this case, the openings 50 a are formed to havediameters 60 μm and 75 μm.

(8) The substrate having the via hole openings 6 formed therein isimmersed in a solution containing 60 g/l of permanganic acid at atemperature of 80° C. for 10 minutes to melt and remove epoxy resinparticles existing on the surfaces of the interlayer resin insulatinglayers 2, thereby forming roughened surfaces 50 a on the surfaces of therespective interlayer resin insulating layers 50 including the innerwalls of the via hole openings 50 a (FIG. 2(E)).

(9) Next, the substrate which has been subjected to the above-statedtreatments is immersed in neutralizer (manufactured by ShipleyCorporation) and then washed.

Further, a palladium catalyst is added to the surfaces of the roughenedsubstrate (a roughening depth of 3 μm), thereby attaching catalystnuclei to the surfaces of the interlayer resin insulating layers and theinner wall surfaces of the via hole openings. Namely, the substrate isimmersed in a catalytic solution containing palladium chloride (PbCl2)and stannous chloride (SnCl2) and palladium metal is precipitated,thereby attaching the catalyst.

(10) The substrate to which the catalyst is attached is immersed in anelectroless copper plating aqueous solution having the followingcomposition and electroless copper plated films having a thickness of0.3 to 3.0 μm are formed on the entire roughened surfaces, therebyobtaining the substrate having electroless copper plated films 52 formedon the surfaces of the interlayer resin insulating layers 50 includingthe inner walls of the via hole openings 50 a (FIG. 3(A)). [Electrolessplating aqueous solution] NiSO4 0.003 mol/l Tartaric acid 0.200 mol/lCopper sulfate 0.032 mol/l HCHO 0.050 mol/l NaOH 0.100 mol/l α,α′-bipyridyl 100 mg/l Polyethylene glycol (PEG) 0.10 g/l[Electroless Plating Conditions]

45 minutes and a solution temperature of 34° C.

(11) Commercially available sensitive dry films are bonded to thesubstrate on which the electroless copper plated films 52 are formed, amask is put on the substrate, the substrate is exposed at 110 mJ/cm² anddeveloped with a 0.8% sodium carbonate aqueous solution, therebyproviding plating resists 54 having a thickness of 25 μm (FIG. 3(B)).

(12) Next, the substrate is cleaned and degreased with water at 50° C.,washed with water at 25° C., cleaned with sulfuric acid andelectroplated under the following conditions, thereby formingelectroplated copper films 56 having a thickness of 20 μm on portions onwhich the plating resists 54 are not formed (FIG. 3(C)). [Electroplatingsolution] Sulfuric acid 2.24 mol/l Copper sulfate 0.26 mol/l Additive(Kalapacid GL 19.5 ml/l manufactured by Atotech Japan)

[Electroplating conditions] Current density 1 A/dm² Time 65 minutesTemperature 22 ± 2° C.

(13) After peeling off the plating resists 3 with 5% KOH, theelectroless plated films under the plating resist are etched, molten andremoved with a solution mixture of sulfuric acid and hydrogen peroxide,thus forming independent conductor circuits 58 and via holes 60 (FIG.3(D)).

(14) The same treatment as that of (5) is performed to form roughenedsurfaces 58α and 60α on the surfaces of the conductor circuits 58 andthe via holes 60. The thickness of the upper layer conductor circuits 58is 15 μm (FIG. 4(A)). However, the upper layer conductor circuits may beformed to have a thickness between 5 and 25 μm.

(15) The steps (6) to (14) stated above are repeated, thereby formingfurther upper layer conductor circuits and a multilayer wiring board isobtained (FIG. 4(B)).

(16) Next, 45.67 parts by weight of oligomer (molecular weight: 4000)which is obtained by forming 50% of epoxy groups of 60 parts by weightof cresol novolac type epoxy resin (manufactured by Nippon Kayaku Co.,Ltd.) dissolved in diethylene glycol dimethyl ether (DMDG) into anacrylic structure and which imparts photosensitive characteristic, 16.0parts by weight of 80 wt % of bisphenol A type epoxy resin (manufacturedby Yuka Shell, product name: Epicoat 1001) dissolved in methylethylketone, 1.6 parts by weight of imidazole hardening agent (manufacturedby Shikoku Chemicals, product name: 2E4MZ-CN), 4.5 parts by weight ofbifunctional acryl monomer which is photosensitive monomer (manufacturedby Kyoei Chemical, product name: R604) 1.5 parts by weight of polyhydricacryl monomer (manufactured by Kyoei Chemical, product name: DPE6A), and0.71 parts by weight of dispersing defoaming agent (manufactured bySannopuko KK, product name: S-65) are input in the container, agitatedand mixed to prepare a mixture composition. 1.8 parts by weight ofbenzophenone (manufactured by Kanto Chemical) serving as photoinitiatorand 0.2 parts by weight of Michler's ketone (manufactured by KantoChemical) serving as photosensitizer are added to the mixturecomposition, thereby obtaining a solder resist composition adjusted tohave a viscosity of 2.0 Pa.s at 25° C.

The viscosity is measured by using the No. 4 rotor of a B-typeviscometer (manufactured by Tokyo Keiki, DVL-B type) when the velocityis 60 min-l, and using the No. 3 rotor thereof when the velocity is 6min-l.

(17) Next, after the above-stated solder resist composition 70 is coatedon each surface of the multilayer wiring board by a thickness of 20 μm,and dried under conditions of 70° C. for 20 minutes and 70° C. for 30minutes (FIG. 4(C)), a photomask on which a pattern of solder resistopening portions are drawn and which has a thickness of 5 mm, is fixedlyattached to each solder resist layer 70, exposed with ultraviolet raysof 1000 mJ/cm², and developed with a DMTG solution, thereby formingopening portions 71 having a diameter of 200 μm (FIG. 5(A)).

Further, heat treatments are conducted at 80° C. for 1 hour, at 100° C.for 1 hour, at 120° C. for 1 hour, and at 150° C. for 3 hours,respectively, to harden the solder resist layers, thus forming solderresist pattern layers each having opening portions and a thickness of 15to 25 μm. As the solder resist composition, a commercially availablesolder resist composition can be also used.

(18) Next, the substrate having the solder resist layers 70 formedthereon is immersed in an electroless nickel plating solution containingnickel chloride (2.3×10⁻¹ mol/l), sodium hypophosphite (2.8×10⁻¹ mol/l)and sodium citrate (1.6×10⁻¹ mol/l) and a pH of 4.5 for 20 minutes,thereby forming nickel plated layers 72 having a thickness of 5 μm inthe opening portions 71. Further, the resultant substrate is immersed inan electroless gold plating solution containing potassium gold cyanide(7.6×10⁻³ mol/l), ammonium chloride (1.9×10⁻¹ mol/l), sodium citrate(1.2×10⁻¹ mol/l) and sodium hypophosphite (1.7×10⁻¹ mol/l) at 80° C. for7.5 minutes, thereby forming gold plated layers 74 each having athickness of 0.03 μm on the respective nickel plated layers 72 (FIG.5(B)). Alternatively, a single tin or noble metal (gold, silver,palladium, platinum or the like) layer may be formed in stead of thenickel-gold layers.

(19) Thereafter, tin-lead containing solder paste is printed on eachopening 71 of the solder resist layer 70 on one surface of the substrateon which surface the IC chip is mounted, tin-antimony containing solderpaste is further printed on each opening on the other surface of thesubstrate, and solder bumps (solder bodies) are formed by conductingreflow at 200° C., thereby manufacturing a multilayer printed wiringboard including solder bumps 76U and 76D (FIG. 6).

The IC chip 90 is attached to the multilayer printed wiring board andchip capacitors 98 are mounted thereon through the solder bumps 76U.Further, the multilayer printed wiring board is attached to the daughterboard 94 through the solder bumps 76D (FIG. 7).

Embodiment 1-2

A multilayer printed wiring board is manufactured in the same manner asthat of Embodiment 1-1 described above with reference to FIG. 6 exceptfor the following respects:

Thickness of conductor layers of a core substrate: 55 μm; thickness of apower supply layer of the core substrate: 55 μm; and thickness ofconductor layers of interlayer insulating layers: 15 μm.

Embodiment 1-3

A multilayer printed wiring board is manufactured in the same manner asthat of Embodiment 1-1 except. for the following respects:

Thickness of conductor layers of a core substrate: 75 μm; thickness of apower supply layer of the core substrate: 75 μm; and thickness ofconductor layers of interlayer insulating layers: 15 μm.

Embodiment 1-4

A multilayer printed wiring board is manufactured in the same manner asthat of Embodiment 1 except for the following respects:

Thickness of conductor layers of a core substrate: 180 μm; thickness ofa power supply layer of the core substrate: 180 μm; and thickness ofconductor layers of interlayer insulating layers: 6 μm.

Embodiment 1-5

A multilayer printed wiring board is manufactured in the same manner asthat of Embodiment 1-1 except for the following respects:

Thickness of conductor layers of a core substrate: 18 μm; thickness of apower supply layer of the core substrate: 18 μm; and thickness ofconductor layers of interlayer insulating layers: 15 μm.

In Embodiment 1, the conductor layer serving as the power supply layerof the core substrate and those of the interlayer insulating layerswhich satisfy 1<(thickness of conductor layer as power supply layer ofcore substrate/thickness of conductor layers of interlayer insulatinglayers)≦40 are set for appropriate examples of Embodiment 1 while thosewhich satisfy (thickness of conductor layer as power supply layer ofcore substrate/thickness of conductor layers of interlayer insulatinglayers)≦1 are set for a comparative example. Furthermore, those whichsatisfy (thickness of conductor layer as power supply layer of coresubstrate/thickness of conductor layers of interlayer insulatinglayers)>40 are set for a reference example.

Embodiment 2 Ceramic Substrate

A multilayer printed wiring board according to Embodiment 2 will bedescribed.

In Embodiment 1 described above with reference to FIG. 6, the coresubstrate is formed out of insulating resin. In Embodiment 2, bycontrast, a core substrate is an inorganic hard substrate made ofceramic, glass, ALN, mullite or the like. Since the other constitutionsare the same as those in Embodiment 1 described above with reference toFIG. 6, they will not be described and illustrated herein.

On the multilayer printed wiring board in Embodiment 2 similarly toEmbodiment 1, the conductor layers 34P and 34P on the core substrate 30and the conductor layers 24 in the core substrate are formed out ofmetal such as copper or tungsten and the conductor circuits 58 on theinterlayer resin insulating layers 50 and the conductor circuits 158 onthe interlayer resin insulating layers 150 are formed out of copper.This Embodiment 2 attains the same advantages as those of Embodiment 1.The conductor layers of the core substrate, the power supply layerthereof and the interlayer insulating layers are formed to have the samethicknesses as those of Embodiment 1. Further, in Embodiment 2, theconductor layer serving as the power supply layer of the core substrateand those of the interlayer insulating layers which satisfy 1<(thicknessof conductor layer as power supply layer of core substrate/thickness ofconductor layers of interlayer insulating layers)≦40 are set forappropriate examples of Embodiment 1 while those which satisfy(thickness of conductor layer as power supply layer of coresubstrate/thickness of conductor layers of interlayer insulatinglayers)≦1 are set for a comparative example. Furthermore, those whichsatisfy (thickness of conductor layer as power supply layer of coresubstrate/thickness of conductor layers of interlayer insulatinglayers)>40 are set for a reference example.

Embodiment 2-1

A multilayer printed wiring board is manufactured in the same manner asthat of Embodiment 2 stated above except for the following respects:

Thickness of conductor layers of a core substrate: 30 μm; thickness of apower supply layer of the core substrate: 30 μm; and thickness ofconductor layers of interlayer insulating layers: 15 μm.

Embodiment 2-2

A multilayer printed wiring board is manufactured in the same manner asthat of Embodiment 2 stated above except for the following respects:

Thickness of conductor layers of a core substrate: 50 μm; thickness of apower supply layer of the core substrate: 50 μm; and thickness ofconductor layers of interlayer insulating layers: 15 μm.

Embodiment 2-3

A multilayer printed wiring board is manufactured in the same manner asthat of Embodiment 2 stated above except for the following respects:

Thickness of conductor layers of a core substrate: 75 μm; thickness of apower supply layer of the core substrate: 75 μm; and thickness ofconductor layers of interlayer insulating layers: 15 μm.

Embodiment 2-4

A multilayer printed wiring board is manufactured in the same manner asthat of Embodiment 2 stated above except for the following respects:

Thickness of conductor layers of a core substrate: 180 μm; thickness ofa power supply layer of the core substrate: 180 μm; and thickness ofconductor layers of interlayer insulating layers: 6 μm.

Embodiment 3 Metal Core Substrate

A multilayer printed wiring board according to Embodiment 3 will bedescribed with reference to FIGS. 8 and 9.

In Embodiment 1 described above with reference to FIG. 6, the coresubstrate is formed out of a resin board. In Embodiment 3, by contrast,a core substrate is formed out of a metallic plate.

FIG. 8 shows the cross section of the multilayer printed wiring board 10according to Embodiment 3 and FIG. 9 shows a state in which an IC chip90 is attached to the multilayer printed wiring board 10 shown in FIG. 8and in which the board 10 is mounted on a daughter board 94.

As shown in FIG. 8, the core substrate 30 of the multilayer printedwiring board 10 is made of a metallic plate and used as a power supplylayer. Interlayer resin insulating layers 50 on which via holes 60 andconductor circuits 58 are arranged are formed on the both surfaces ofthe core substrate 30, respectively and interlayer resin insulatinglayers 150 on which via holes 160 and conductor circuits 158 arearranged are formed on the respective interlayer resin insulating layers50. In the pass-through holes 33 of the core substrate 30, through holes36 are formed, and cover plating layers 37 are arranged on the both endsof the via holes. Solder resist layers 70 are formed on the upper layersof the via holes 160 and the conductor circuit 158 and bumps 76U and 76Dare formed on the via holes 160 and the conductor circuits 158 throughthe opening portions 71 of the solder resist layers 70, respectively.

As shown in FIG. 9, solder bumps 76U on the upper surface of themultilayer printed wiring board 10 are connected to lands 92 of the ICchip 90. Further, chip capacitors 98 are mounted on the board 10. Solderbumps 76D on the lower surface thereof are connected to lands 96 of thedaughter board 94.

Here, the core substrate 30 is formed to have a thickness of 200 to 600μn. The metallic plate is formed to have a thickness between 15 and 300μm. The conductor layers of the interlayer resin insulating layers maybe formed to have a thickness between 5 and 25 μm. However, thethickness of the metallic layer may exceed the above range.

Embodiment 3 attains the same advantages as those of Embodiment 1.

Embodiment 3-1

A multilayer printed wiring board is formed in the same manner asEmbodiment 3 described above with reference to FIG. 8 except for thefollowing respects:

Thickness of a core substrate: 550 μm; thickness of a power supply layerof the core substrate: 35 μm; and thickness of conductor layers ofinterlayer insulating layers: 15 μm.

Embodiment 3-2

A multilayer printed wiring board is formed in the same manner asEmbodiment 3 except for the following respects:

Thickness of a core substrate: 600 μm; thickness of a power supply layerof the core substrate: 55 μm; and thickness of conductor layers ofinterlayer insulating layers: 15 μm.

Embodiment 3-3

A multilayer printed wiring board is formed in the same manner asEmbodiment 3 except for the following respects:

Thickness of a core substrate: 550 μm; thickness of a power supply layerof the core substrate: 100 μn; and thickness of conductor layers ofinterlayer insulating layers: 10 μm.

Embodiment 3-4

A multilayer printed wiring board is formed in the same manner asEmbodiment 3 except for the following respects:

Thickness of a core substrate: 550 μm; thickness of a power supply layerof the core substrate: 180 μm; and thickness of conductor layers ofinterlayer insulating layers: 6 μm.

Embodiment 3-5

A multilayer printed wiring board is formed in the same manner asEmbodiment 3 except for the following respects:

Thickness of a core substrate: 550 μm; thickness of a power supply layerof the core substrate: 240 μm; and thickness of conductor layers ofinterlayer insulating layers: 6 μm.

In Embodiment 3, the conductor layer serving as the power supply layerof the core substrate and those of the interlayer insulating layerswhich satisfy 1<(thickness of conductor layer as power supply layer ofcore substrate/thickness of conductor layers of interlayer insulatinglayers)≦40 are set for appropriate examples of Embodiment 3 while thosewhich satisfy (thickness of conductor layer as power supply layer ofcore substrate/thickness of conductor layers of interlayer insulatinglayers)≦1 are set for a comparative example. Furthermore, those whichsatisfy (thickness of conductor layer as power supply layer of coresubstrate/thickness of conductor layers of interlayer insulatinglayers)>40 are set for a reference example.

Embodiment 4 Multilayer Core Substrate

A multilayer printed wiring board according to Embodiment 4 will bedescribed with reference to FIGS. 10 and 11.

In Embodiment 1 described above with reference to FIG. 6, the coresubstrate comprises a single board. In Embodiment 4, by contrast, a coresubstrate comprises multilayer boards and conductor layers are providedin the multilayer boards.

FIG. 10 shows the cross section of the multilayer printed wiring board10 according to Embodiment 4 and FIG. 11 shows a state in which an ICchip 90 is attached to the multilayer printed wiring board 10 shown inFIG. 10 and in which the board 10 is mounted on a daughter board 94. Asshown in FIG. 10, on the multilayer printed wiring board 10, conductorcircuits 34 and conductor layers 34P are formed on the front and rearsurfaces of the core substrate 30, respectively and conductor layers 24are formed in the core substrate 30. The conductor layers 34P and 24 areformed as power supply plane layers. The conductor layers 34P and 24 areconnected to one another by conductive posts 26. (The conductive postsmean herein via holes such as through holes or non-through holes(including blind through holes and blind via holes) or holes filled withthrough hole or via hole conductive material.) In addition, aninterlayer resin insulating layer 50 on which via holes 60 and conductorcircuits 58 are formed and an interlayer resin insulating layer 150 onwhich via holes 160 and conductor circuits 158 are formed are providedon each of the conductor layers 34P. Solder resist layers 70 are formedon upper layers of the via holes 160 and the conductor circuits 158, andbumps 76U and 76D are formed on the via holes 160 and the conductorcircuits 158 through the opening portions 71 of the solder resist layers70, respectively.

As shown in FIG. 11, solder bumps 76U on the upper surface of themultilayer printed wiring board 10 are connected to lands 92 of the ICchip 90. Further, chip capacitors 98 are mounted on the board 10. Solderbumps 76D on the lower surface thereof are connected to lands 96 of thedaughter board 94. Here, the conductor circuits 34 and the conductorlayers 34P, 34P on the core substrate 30 and the conductor layers 24 inthe core substrate are formed and conductor circuits 58 on interlayerresin insulating layers 50 and conductor circuits 158 on interlayerresin insulating layers 150 are formed. The conductor layers 34P and 24of the core substrate are formed to have thicknesses between 1 and 250μm and the conductor layers formed on the core substrate and serving asthe power supply layers are formed to have a thickness between 1 and 250μm. The thickness of each conductor layer in this case is the sum of thethicknesses of the power supply layers of the core substrate. This meansthat the thickness of the conductor layer is the sum of the thickness ofthe conductor layer 34 on the inner layer and that of the conductorlayer 24 on the surface layer. This does not mean that the thicknessesof the layers serving as signal lines are added together. In Embodiment4, by summing the thicknesses of the three conductor layers 34P, 34P and24, the same advantages as those of Embodiment 1 are attained. Thethickness of the power supply layers may exceed the above range.

In Embodiment 4, the conductor layer serving as the power supply layerof the core substrate and those of the interlayer insulating layerswhich satisfy 1<(sum of thickness of conductor layer as power supplylayer of core substrate/thickness of conductor layers of interlayerinsulating layers)≦40 are set for appropriate examples of Embodiment 4while those which satisfy (sum of thickness of conductor layer as powersupply layer of core substrate/thickness of conductor layers ofinterlayer insulating layers)≦1 are set for a comparative example.Furthermore, those which satisfy (sum of thickness of conductor layer aspower supply layer of core substrate/thickness of conductor layers ofinterlayer insulating layers)>40 are set for a reference example.

Embodiment 4-1

A multilayer printed wiring board is formed in the same manner as thatof Embodiment 4 stated above with reference to FIG. 10 except for thefollowing respects:

Thickness of conductor layers (power supply layers) of the coresubstrate: 15 μm

Thicknesses of intermediate conductor layers (power supply layers): 20μm

Sum of thicknesses of power supply layers of the core substrate: 50 μm

Thickness of conductor layers of interlayer insulating layers: 15 μm.

Embodiment 4-2

A multilayer printed wiring board is formed in the same manner as thatof Embodiment 4 except for the following respects.

Thickness of conductor layers (power supply layers) of the coresubstrate: 20 μm

Thicknesses of intermediate conductor layers (power supply layers): 20μm

Sum of thicknesses of power supply layers of the core substrate: 60 μm

Thickness of conductor layers of interlayer insulating layers: 15 μm.

Embodiment 4-3

A multilayer printed wiring board is formed in the same manner as thatof Embodiment 4 except for the following respects.

Thickness of conductor layers (power supply layers) of the coresubstrate: 25 μm

Thicknesses of intermediate conductor layers (power supply layers): 25μm

Sum of thicknesses of power supply layers of the core substrate: 75 μm

Thickness of conductor layers of interlayer insulating layers: 15 μm.

Embodiment 4-4

A multilayer printed wiring board is formed in the same manner as thatof Embodiment 4 except for the following respects.

Thickness of conductor layers (power supply layers) of the coresubstrate: 50 μm

Thicknesses of intermediate conductor layers (power supply layers): 100μm

Sum of thicknesses of power supply layers of the core substrate: 200 μm

Thickness of conductor layers of interlayer insulating layers: 10 μm.

Embodiment 4-5

A multilayer printed wiring board is formed in the same manner as thatof Embodiment 4 except for the following respects.

Thickness of conductor layers (power supply layers) of the coresubstrate: 55 μm

Thicknesses of intermediate conductor layers (power supply layers): 250μm

Sum of thicknesses of power supply layers of the core substrate: 360 μm

Thickness of conductor layers of interlayer insulating layers: 12 μm.

Embodiment 4-6

A multilayer printed wiring board is formed in the same manner as thatof Embodiment 4 except for the following respects.

Thickness of conductor layers (power supply layers) of the coresubstrate: 55 μm

Thicknesses of intermediate conductor layers (power supply layers): 250μm

Sum of thicknesses of power supply layers of the core substrate: 360 μm

Thickness of conductor layers of interlayer insulating layers: 9 μm.

Embodiment 5 Multilayer Core Substrate

A multilayer printed wiring board according to Embodiment 5 of thepresent invention will be described with reference to FIGS. 10 to 11.The configuration of a multilayer printed wiring board 10 according toEmbodiment 5 will first be described with reference to FIGS. 19 and 20.FIG. 19 shows the cross section of the multilayer printed wiring board10 and FIG. 20 shows a state in which an IC chip 90 is attached to themultilayer printed wiring board 10 shown in FIG. 19 and in which theboard 10 is mounted on a daughter board 94. As shown in FIG. 19, amultilayer printed wiring board 10 employs a multilayer core substrate30. A conductor circuit 34 and a conductor layer 34P are formed on thefront surface of the multilayer core substrate 30 and a conductorcircuit 34 and a conductor layer 34E are formed on the rear surfacethereof. The upper conductor layer 34P is formed as a power supply planelayer while the lower conductor layer 34E is formed as an earth planelayer. Further, a conductor circuit 16 and a conductor layer 16E on theinner layer are formed on the inside surface of the multilayer coresubstrate 30 while a conductor circuit 16 and a conductor layer 16P areformed on the inside rear surface thereof. The upper conductor layer 16Eis formed as an earth plane layer while the lower conductor layer 16P isformed as a power supply plane layer. Connection to the power supplyplane layer is established by through holes or via holes. The planelayer may comprise a single layer formed on one side or comprise two ormore layers. Preferably, the plane layer comprises two to four layers.Since it is not confirmed that the plane layer comprising four or moreplane layers can improve electric characteristic, the electriccharacteristic of the plane layer comprising four or more layers is thesame as that of the plane layer comprising four layers. Particularly ifthe plane layer comprising two layers, the expansion ratios of thesubstrate can be made uniform and warps less occur in terms of therigidity matching of the multilayer core substrate. An electricallyinsulated metallic plate 12 is contained at the center of the multilayercore substrate 30. (Although the metallic plate 12 serves as a centralmaterial, it is not electrically connected to the through holes, viaholes and the like. The metallic plate 12 mainly serves to improve therigidity of the substrate 30 against warps.) A conductor circuit 16 anda conductor layer 16E are formed on the metallic plate 12 on the frontsurface side of the substrate 30 through an insulating resin layer 14and a conductor circuit 16 and a conductor layer 16P are formed on themetallic plate 12 on the rear surface side of the substrate 30 throughan insulating resin layer 14. Further, a conductor circuit 34 and aconductor layer 34P are formed on the metallic plate 12 on the frontsurface side of the substrate 30 through an insulating resin layer 18and a conductor circuit 34 and a conductor layer 34E are formed on themetallic plate 12 on the rear surface side of the substrate 30 throughan insulating resin layer 18. The front surface side and the rearsurface side of the multilayer core substrate 30 are connected to eachother via through holes 36.

Interlayer resin insulating layers 50 on which via holes 60 andconductor circuits 58 are formed and interlayer resin insulating layers150 on which via holes 160 and conductor circuits 158 are formed arearranged on the conductor layers 34P and 34E on the surfaces of themultilayer core substrate 30, respectively. Solder resist layers 70 areformed on the upper layers of the via holes 160 and the conductorcircuits 158 and bumps 76U and 76D are formed on the via holes 160 andthe conductor circuits 158 through the opening portions 71 of the solderresist layers 70, respectively.

As shown in FIG. 20, solder bumps 76U on the upper surface of themultilayer printed wiring board 10 are connected to lands 92 of the ICchip 90. Further, chip capacitors 98 are mounted on the board 10.External terminals 76D on the lower surface thereof are connected tolands 96 of the daughter board 94. External terminals refer herein toPGA's, BGA's, solder bumps or the like.

The conductor layers 34P and 34E on the front layers of the coresubstrate 30 are formed to have thicknesses of 10 to 60 μm, theconductor layers 16P and 16E are formed on the inner layer to havethicknesses of 10 to 250 μm, the conductor circuits 58 on the interlayerresin insulating layers 50 and the conductor circuits 158 on theinterlayer resin insulating layers 150 are formed to have thicknesses of10 to 25 μm.

On the multilayer printed wiring board according to Embodiment 5, thepower supply layer (conductor layer) 34P on the surface layer of thecore substrate 30, the conductor layers 34, the power supply layer(conductor layer) 16P on the inner layer of the core substrate 30, theconductor layer 16E and the metallic plate 12 are made thick, therebyintensifying the strength of the core substrate. As a result, even ifthe core substrate itself is formed thin, it is possible for thesubstrate itself to relax warps and generated stresses.

Furthermore, by making the conductor layers 34P and 34E and conductorlayers 16P and 16E thick, it is possible to increase the volumes of theconductors themselves. By increasing the volumes, it is possible todecrease the resistance of the conductors.

In addition, by employing the conductor layers 34P and 16P as powersupply layers, it is possible to improve the capability of supplyingpower to the IC chip 90. Due to this, if the IC chip is mounted on themultilayer printed wiring board, it is possible to decrease a loopinductance of the IC chip—the substrate—the power supply. Accordingly,power shortage in an initial operation is decreased to make it difficultto cause power shortage. Even if the IC chip in a higher frequency rangeis mounted on the multilayer printed wiring board, malfunction, error orthe like does not occur in the initial operation. Besides, by employingthe conductor layers 34E and 16E as earth layers, noise does notsuperpose on the signal of the IC chip and the supply of power to the ICchip, thus making it possible to prevent malfunction or error. Bymounting capacitors, the power accumulated in the capacitors can be usedas auxiliary power, making it difficult to cause power shortage. Byproviding the capacitors right under the IC chip, in particular, theeffect (of making it difficult to cause power shortage) becomesconspicuous. This is because the capacitors right under the IC chipenables shortening wiring lengths on the multilayer printed wiringboard.

In Embodiment 5, the multilayer core substrate 30 has the thickconductor layers 16P and 16E on the inner layer and the thin conductorlayers 34P and 34E on the surface of the substrate 30, and the innerlayer conductor layers 16P and 16E and the surface layer conductorlayers 34P and 34E are employed as the power supply conductor layers andthe earth conductor layers, respectively. Namely, even if the thickconductor layers 16P and 16E are arranged on the inner layer side of thesubstrate 30, the resin layers covering the conductor layers are formed.Due to this, it is possible to cancel irregularities derived from theconductor layers and thereby flatten the surface of the multilayer coresubstrate 30. Therefore, even if the thin conductor layers 34P and 34Eare arranged on the surfaces of the multilayer core substrate 30 so asnot to generate waviness on the conductor layers 58 and 158 of therespective interlayer resin insulating layers 50 and 150, it is possibleto secure sufficient thickness as that of the conductor layers of thecore by the sum of the thicknesses of the conductor layers 16P and 16Eon the inner layer. Since no waviness occurs, no problem occurs to theimpedances of the conductor layers on the interlayer insulating layers.By employing the conductor layers 16P and 34P as the power supplyconductor layers and the conductor layers 16E and 34E as the earthconductor layers, it is possible to improve the electric characteristicsof the multilayer printed wiring board.

Furthermore, by arranging the signal line 16 between the conductorlayers 34P and 16P (on the same layer as that of the conductor layer16E) in the core substrate, it is possible to form a micro-stripstructure. Likewise, by arranging the signal line 16 between theconductor layers 16E and 34E (on the same layer as that of the conductorlayer 16P), it is possible to form a micro-strip structure. By formingthe micro-strip structures, it is possible to decrease inductance and tomatch impedances to one another. Due to this, it is possible tostabilize the electric characteristics of the multilayer printed wiringboard.

That is to say, the thicknesses of the conductor layers 16P and 16E onthe inner layer of the core substrate are set larger than those of theconductor layers 58 and 158 on the interlayer insulating layers 50 and150. By doing so, even if the thin conductor layers 34E and 34P arearranged on the surfaces of the multilayer core substrate 30, it ispossible to secure sufficient thickness as that of the conductor layersof the core by adding the thicknesses of the thick conductor layers 16Pand 16E on the inner layer. The thickness ratio of the conductor layerspreferably satisfies 1<(conductor layer on inner layer of core/conductorlayer of insulating layer)≦40. More preferably, the thickness ratiosatisfies 1.2≦(conductor layer on inner layer of core/conductor layer ofinsulating layer)≦30.

The multilayer core substrate 30 is constituted so that the conductorlayers 16P and 16E as inner layer is formed on each surface of anelectrically isolated metallic plate 12 through a resin layer 14 and sothat the conductor layers 34P and 34E on the surface layer is formedoutside of the conductor layers 16P and 16E as the inner layer throughthe resin layer 18. By arranging the electrically insulated metallicplate 12 on the central portion of the substrate, it is possible tosecure sufficient mechanical strength. Further, by forming the conductorlayers 16P and 16E on the inner layer of the both surfaces of themetallic plate 12 through the resin layers 14, respectively and theconductor layers 34P and 34E on the surface layer on the outside of theconductor layers 16P and 16E as the inner layer on the both surfaces ofthe metallic plate 12 through the resin layers 18, respectively, it ispossible to impart symmetry to the both surfaces of the metallic plate12 and to prevent the occurrence of warps, waviness and the like in aheat cycle and the like.

FIG. 21 shows a modification of Embodiment 5. In this modification,capacitors 98 are arranged right under the IC chip 90. Due to this, thedistance between the IC chip 90 and the capacitor 98 is short, making itpossible to prevent the voltage drop of the power supplied to the ICchip 90.

Next, a method for manufacturing the multilayer printed wiring board 10shown in FIG. 19 will be described with reference to FIGS. 12 to 18.

(1) Formation of Metallic Layer

Openings 12 a are provided in an inner layer metallic layer (metallicplate) 12 having a thickness of 50 to 400 μm as shown in FIG. 12(A) topenetrate the front and rear surfaces of the layer 12 (FIG. 12(B)). Asthe material of the metallic layer, a material containing a mixture ofcopper, nickel, zinc, aluminum, iron and the like can be used. Theopenings 12 a are formed by punching, etching, drilling, a laser or thelike. Depending on cases, metallic films 13 may be coated on the entiresurfaces of the metallic layer 12 having the openings 12 a formedtherein by electroplating, electroless plating, substitutional platingor sputtering (FIG. 12(C)). The metallic plate 12 may comprise a singlelayer or a plurality of layers of two or more layers. In addition, themetallic films 13 preferably have curves formed on the corners of theopenings 12 a. The curves can eliminate points at which stresses areconcentrated and make it more difficult to cause defects such as cracksand the like around the points.

(2) Formation of Insulating Layers on Inner Layer

Insulating resin is used to cover the entire surfaces of the metalliclayer 12 and fill up the openings 12 a. For example, the metallic plate12 is put between resin films in a B stage state of a thickness of about30 to 200 μm, the resin films are thermally pressed and hardened,whereby insulating rein layers 14 can be formed (FIG. 12(D)). Dependingon cases, the insulating rein layers 14 may be formed out of films afterapplying resin, applying resin and press-fitting the resin films orapplying the resin only to the opening portions.

As the material of the insulating resin layers 14, a prepreg having acore material such as glass cloth impregnated with thermosetting resinsuch as polyimide resin, epoxy resin, phenol resin or BT resin ispreferable. The other resin may be used.

(3) Bonding of Metallic Foils

Metallic layers 16α on the inner layer are formed on the both surfacesof the metallic layer 12 covered with the resin layers 14, respectively(FIG. 12(E)). By way of example, metallic foils having a thickness of 12to 275 μm are built on the both surfaces thereof. As an alternative tothe method for forming the metallic foils, a one-sided copper-cladlaminate is built up on each surface of the metallic layer 12. Thelaminate can be formed on the metallic foils by plating or the like.

(4) Formation of Circuits of Metallic Layer on the Inner Layer

Two or more layers may be formed. The metallic layer may be formed bythe additive method.

Through a denting method, etching steps and the like, conductor layers16, 16P and 16E on the inner layer are formed from the inner layermetallic layer 16α (FIG. 12(F)). The inner layer conductor layers areformed to have thicknesses of 10 to 250 μm. Alternatively, thethicknesses may exceed the range.

(5) Formation of Insulating Layers as Outer Layers

Insulating resin is used to cover the entire surfaces of the inner layerconductor layers 16, 16P and 16E and fill up the gaps between thecircuits of outer layer metal. By way of example, outer layer insulatingresin layers 18 are formed by putting the metallic plate between resinfilms in a B stage state of a thickness of about 30 to 200 μm, thermallypress-fitting and hardening the resin films (FIG. 13(A)). Depending oncases, the outer layer insulating resin layers 18 may be formed out offilms after applying resin, applying resin and press-fitting the resinfilms or applying the resin only to the opening portions. By applyingpressure, it is possible to flatten the surfaces of the layers 18.

(6) Bonding of Outermost Layer Metallic Foils

Outermost metallic layers 34β are formed on the both surfaces of thesubstrate covered with the outer layer insulating resin layers 18 (FIG.13(B)). By way of example, metallic foils having a thickness of 10 to275 μm are built up on the both surfaces of the substrate. As analternative to the method for forming the metallic foils, one-sidedcopper-clad laminates are built up. Two or more layers of the laminatesmay be formed on the metallic foils. The metallic layers may be formedby the additive method.

(7) Formation of Through Holes

Pass-through holes 36α for through holes having opening diameter of 50to 400 μm are formed to penetrate the front and rear surfaces of thesubstrate (FIG. 13(C)). As a formation method, the holes are formed bydrilling, a laser or a combination of drilling and the laser. (The holesare opened in the outermost insulating layers by the laser, and thenmaybe penetrated through the substrate by drilling while using the holesopened by the laser as target marks.) The forms of the holes arepreferably those having linear sidewalls. Depending on cases, the holesmay be tapered.

To secure the conductive properties of the through holes, it ispreferable to form plated films 22 in the respective pass-through holes36α for the through holes and roughen the surfaces of the plated films22 (FIG. 13(D)), and then to fill the holes with resin filler 23 (FIG.13(E)). As the resin filler, either an electrically insulated resinmaterial (e.g., a resin material containing a resin component, hardeningagent, particles and the like) or a conductive material holdingelectrical connection by metallic particles (e.g., a conductive materialcontaining metallic particles such as gold or copper particles, a resinmaterial, hardening agent and the like) can be used.

As plating, electroplating, electroless plating, panel plating(electroless plating and electroplating) or the like may be performed.The plated films 22 are formed by plating metals containing copper,nickel, cobalt, phosphorus or the like. The thicknesses of the platedmetals are preferably 5 to 30 μm.

The resin filler 23 filled in the pass-through holes 36 a for thethrough holes is preferably made of an insulating material comprising aresin material, hardening agent, particles and the like. As theparticles, inorganic particles such as silica or alumina particles canbe used solely, metallic particles such as gold, silver or copperparticles can be used solely, resin particles can be used solely or theinorganic particles, the metallic particles and the resin particles canbe mixed together. The particles equal in particle size from 0.1 to 5 μmor different in particle size from 0.1 to 5 μm can be mixed. As theresin material, thermosetting resin such as epoxy resin (e.g., bisphenoltype epoxy resin or novolac type epoxy resin and the like) or phenolresin, ultraviolet setting resin having a photosensitive property,thermoplastic resin or the like may be used solely or mixed together. Asthe hardening agent, imidazole based hardening agent, amine basedhardening agent or the like can be used. Alternatively, hardening agentcontaining hardening stabilizer, reaction stabilizer, particles and thelike may be used. In the latter case, the resin filler is replaced byconductive paste made of a conductive material comprising metallicparticles, a resin component, hardening agent and the like. Depending oncases, metallic films having a conductive property may be formed on thesurface layers of an insulating material such as solder or insulatingresin. It is also possible to fill the pass-through holes 36 a forthrough holes with plated members. Since the conductive paste ishardened and contracted, depressed portions are sometimes formed on thesurface layers.

(8) Formation of Outermost Layer Conductor Circuits

Cover plated members 25 may be formed right on the through holes 36 bycoating plated films on the entire surfaces of the substrate (FIG.14(A)). Thereafter, outer layer conductor circuits 34, 34P and 34E areformed through the denting method, etching steps and the like (FIG.14(B)). As a result, the multilayer core substrate 30 is completed.

At this time, although not shown in the drawings, the electricalconnection of the outer conductor circuits to inner conductor layers 16and the like of the multilayer core substrate may be established by viaholes, blind through holes or blind via holes.

Thereafter, similarly to Embodiment 1 described above with reference toFIGS. 1(C) to 5, interlayer resin insulating layers 50 and 150 andconductor circuits 58 and 158 are formed on the multilayer coresubstrate 30.

(9) The multilayer core substrate 30 on which the conductor circuits 34have been formed thereon is subjected to a blackening treatment and areduction treatment, thereby forming roughened surfaces 348 on theentire surfaces of the conductor circuits 34 and the conductor layers34P and 34E (FIG. 14(C)).

(10) Layers of the resin filler 40 are formed on the conductor circuitunformed portions of the multilayer core substrate 30 (FIG. 15(A)).

(11) The one surface of the substrate which has been subjected to theabove treatments is polished by belt sander polishing or the like so asnot to leave the resin filler 40 on the outer edges of the conductorlayers 34P and 34E, and then the entire surfaces of the conductor layers34P and 34E (including the land surfaces of the through holes) arefurther polished by buffing or the like so as to eliminate scratchescaused by the former polishing. A series of polishing operations aresimilarly conducted to the other surface of the substrate. Next, theresin filler 40 is hardened by heat treatments at 100° C. for 1 hour and150° C. for 1 hour (FIG. 15(B)).

The resin filler may not be filled between the conductor circuits. Inthat case, using resin layers such as interlayer insulating layers, theinsulating layers are formed and the portions between the conductorcircuits are filled up.

(12) Etchant is sprayed onto the both surfaces of the multilayer coresubstrate 30 and the surfaces of the conductor circuits 34 and theconductor layers 34P and 34E and the land surfaces and inner walls ofthe through holes 36 are subjected to etching or the like, therebyforming roughened surfaces 36B on the entire surfaces of the conductorcircuits (FIG. 15(C)).

(13) Resin films 50γ for interlayer resin insulating layers are mountedon the both surface of the multilayer core substrate 30, respectively,temporarily press-fitted and cut, and then bonded onto the substrateusing the vacuum laminator, thereby forming interlayer resin insulatinglayers (FIG. 16(A)).

(14) Thereafter, through a mask having pass-through holes having athickness of 1.2 mm formed therein, openings 50 a for via holes areformed to have a diameter of 80 μm in the interlayer resin insulatinglayers 2 by a CO2 gas laser having wavelength of 10.4 μm underconditions of a beam diameter of 4.0 mm, a top hat mode, a pulse widthof 7.9 microseconds, the pass-through hole diameter of the mask of 1.0mm and one shot (FIG. 16(B)).

(15) The multilayer core substrate 30 is immersed in a solutioncontaining 60 g/l of permanganic acid at 80° C. for 10 minutes to formroughened surfaces 50α on the surfaces of the interlayer resininsulating layers 50 including the inner walls of the via hole openings50 a (FIG. 15(C)). The roughened surfaces are formed to have a thicknessbetween 0.1 to 5 μm.

(16) Next, the multilayer core substrate 30 which has been subjected tothe above-stated treatments is immersed in neutralizer (manufactured byShipley Corporation) and then washed.

Further, a palladium catalyst is added to the surfaces of the roughenedsubstrate (a roughening depth of 3 μm), thereby attaching catalystnuclei to the surfaces of the interlayer resin insulating layers and theinner wall surfaces of the via hole openings.

(17) The substrate to which the catalyst is attached is immersed in anelectroless copper plating aqueous solution and electroless copperplated films having a thickness of 0.6 to 3.0 μm are formed on theentire roughened surfaces, thereby obtaining the substrate havingelectroless copper plated films 52 formed on the surfaces of theinterlayer resin insulating layers 50 including the inner walls of thevia hole openings 50 a (FIG. 15(D)).

(18) Commercially available dry films are bonded to the substrate onwhich electroless copper plated films 52 are formed, a mask is put onthe substrate, the substrate is developed and plating resists 54 arethereby provided (FIG. 17(A)). The plating resists having a thickness of10 to 30 μm are used.

(19) Next, the multilayer core substrate 30 is electroplated, therebyforming electroplated copper films 56 having a thickness of 5 to 20 μmare formed on portions in which the plating resists 54 are not formed,respectively (FIG. 17(B)).

(20) After peeling off the plating resists with 5% KOH, the electrolessplated films under the plating resist are etched, molten and removedwith a solution mixture of sulfuric acid and hydrogen peroxide, thusforming independent conductor circuits 58 and via holes 60 (FIG. 17(C)).

(21) Next, the same treatment as that of (12) is conducted to formroughened surfaces 58α and 60α on the surfaces of the conductor circuits58 and via holes 60. The upper conductor circuits 58 are formed to havea thickness of 5 to 25 μm. In this example, the upper conductor circuits58 have a thickness of 15 μm (FIG. 17(D)).

(22) The steps (14) to (21) stated above are repeated, thereby formingfurther upper layer conductor circuits and a multilayer wiring board isobtained (FIG. 18(A)).

(23) Next, after the above-stated solder resist composition 70 is coatedon each surface of the multilayer wiring board by a thickness of 12 to30 μm, and dried under conditions of 70° C. for 20 minutes and 70° C.for 30 minutes (FIG. 18(B)), a photomask on which a pattern of solderresist opening portions are drawn and which has a thickness of 5 mm, isfixedly attached to each solder resist layer 70, exposed withultraviolet rays of 1000 mJ/cm², and developed with a DMTG solution,thereby forming opening portions 71 having a diameter of 200 μm (FIG.18(C)). Further, heat treatments are conducted at 80° C. for 1 hour, at100° C. for 1 hour, at 120° C. for 1 hour, and at 150° C. for 3 hours,respectively, to harden the solder resist layers, thus forming solderresist pattern layers each having opening portions and a thickness of 10to 25 μm.

(24) Next, the substrate on which the solder resist layers 70 are formedis immersed in an electroless nickel plating solution, thereby formingnickel plated layers 72 having a thickness of 5 μm on the openingportions 71, respectively. Furthermore, the substrate is immersed in anelectroless gold plating solution, thereby forming gold plated layers 74having a thickness of 0.03 μm on the respective nickel plated layers 72(FIG. 18(D)). Alternatively, a single tin or noble metal (gold, silver,palladium, platinum or the like) layer may be formed in stead of thenickel-gold layers.

(25) Thereafter, tin-lead containing solder paste is printed on eachopening 71 of the solder resist layer 70 on one surface of the substrateon which surface the IC chip is mounted, tin-antimony containing solderpaste is further printed on each opening on the other surface of thesubstrate, and external terminals are formed by conducting reflow at200° C., thereby manufacturing a multilayer printed wiring boardincluding solder bumps (FIG. 19).

The IC chip 90 is attached to the multilayer printed wiring board andchip capacitors 98 are mounted thereon through the external terminals76U. Further, the multilayer printed wiring board is attached to thedaughter board 94 through the solder bumps 76D (FIG. 20).

In Embodiment 5, the conductor layer serving as the power supply layerof the core substrate and those of the interlayer insulating layerswhich satisfy 1<(thickness of conductor layer as power supplylayer/thickness of conductor layers of interlayer insulating layers)≦40are set for appropriate examples of Embodiment 5 while those whichsatisfy (thickness of conductor layer as power supply layer/thickness ofconductor layers of interlayer insulating layers)≦1 are set for acomparative example. Furthermore, those which satisfy (thickness ofconductor layer as power supply layer/thickness of conductor layers ofinterlayer insulating layers)>40 are set for a reference example.

Embodiment 5-1

The multilayer printed wiring board is manufactured in the same manneras that of Embodiment 5 described above with reference to FIG. 19 exceptfor the following respects:

Thickness of conductor layers on the inner layer of the core substrate:50 μm; thickness of conductor layers as surface layers thereof: 20 μm;

Sum of the thicknesses of the conductor circuits of the core substrate:100 μm

Thickness of the conductor layers of the interlayer insulating layers:15 μm.

The conductor layers on the inner layer and those on the surface layerserve as power supply layers. However, the areas of the surfaceconductor layers are about those of the lands and smaller than those ofthe inner conductor layers, so that the effect of dropping power iscancelled. Due to this, the thicknesses of the two inner conductorlayers are added to the thicknesses of the conductor layers of the coresubstrate.

Embodiment 5-2

The conductor layers on the inner layer and the conductor layers on thesurface layer serve as power supply layers. One surface layer and oneinner layer are electrically connected to each other by a through hole.

Thickness of conductor layers on the inner layer of the core substrate:60 μm; thickness of conductor layers as surface layers thereof: 20 μm;

Sum of the thicknesses of the conductor circuits of the core substrate:80 μm

Thickness of the conductor layers of the interlayer insulating layers:15 μm.

One of the conductor layers on the inner layer and one of the conductorlayers on the surface layer serve as one power supply layer. The areasof the conductor layers as the surface layers are equal to those of theconductor layers on the inner layer. The effect of dropping power isexhibited. Due to this, the sum of the thicknesses of the conductorlayers of the core substrate is the sum of the thicknesses of theconductor layers on the inner layer and those as the surface layers.

Embodiment 5-3

The sum of the thicknesses of the conductor layers of the core substrateis the thickness of the conductor layer on the inner layer.

Thickness of conductor layers on the inner layer of the core substrate:75 μm; thickness of conductor layers as surface layers thereof: 20 μm;

Sum of the thicknesses of the conductor circuits of the core substrate:150 μm

Thickness of the conductor layers of the interlayer insulating layers:15 μm.

The conductor layers on the inner layer and those on the surface layerserve as power supply layers. However, the areas of the surfaceconductor layers are about those of the lands and smaller than those ofthe inner conductor layers, so that the effect of dropping power iscancelled. Due to this, the sum of the thicknesses of the conductorcircuits of the core substrate is the thicknesses of the one innerconductor layer the thicknesses of the two inner conductor layers areadded to the thicknesses of the conductor layers of the core substrate.

Embodiment 5-4

A multilayer printed wiring board is formed in the same manner as thatof Embodiment 5-3 except for the following respects.

Thickness of conductor layers on the inner layer of the core substrate:200 μm; thickness of conductor layers as surface layers thereof: 20 μm;

Sum of the thicknesses of the conductor circuits of the core substrate:200 μm

Thickness of the conductor layers of the interlayer insulating layers:10 μm.

The sum of the thicknesses of the conductor circuits of the coresubstrate is the sum of the thicknesses of the conductor layers on theinner layer.

Embodiment 5-5

A multilayer printed wiring board is formed in the same manner as thatof Embodiment 5-3 except for the following respects.

Thickness of conductor layers on the inner layer of the core substrate:240 μm; thickness of conductor layers as surface layers thereof: 20 μm;

Sum of the thicknesses of the conductor circuits of the core substrate:240 μm

Thickness of the conductor layers of the interlayer insulating layers: 8μm.

The sum of the thicknesses of the conductor circuits of the coresubstrate is the sum of the thicknesses of the conductor layers on theinner layer.

Embodiment 5-6

A multilayer printed wiring board is formed in the same manner as thatof Embodiment 5-3 except for the following respects.

Thickness of conductor layers on the inner layer of the core substrate:250 μm; thickness of conductor layers as surface layers thereof: 25 μm;

Sum of the thicknesses of the conductor circuits of the core substrate:300 μm

Thickness of the conductor layers of the interlayer insulating layers:7.5 μm.

Embodiment 6 Capacitor Included Core Substrate

A multilayer printed wiring board according to Embodiment 6 will bedescribed with reference to FIGS. 22 and 23.

On the multilayer printed wiring board according to Embodiment 6, chipcapacitors 20 are included in the core substrate 30.

FIG. 22 is a cross-sectional view of the multilayer printed wiring board10 according to Embodiment 6 and FIG. 23 shows a state in which the ICchip 90 is attached to the multilayer printed wiring board 10 shown inFIG. 22. As shown in FIG. 22, the core substrate 30 of the multilayerprinted wiring board 10 comprises a resin substrate 30A and resin layers30B. The resin substrate 30A is provided with openings 31 a forcontaining the capacitors 20, respectively. The electrodes of thecapacitors 20 are connected to one another by via holes 33 provided inthe resin layer 30B. A conductor layer 34P for forming conductorcircuits 34 and a power supply layer is formed on the upper surface ofthe core substrate 30, and interlayer resin insulating layers 50 onwhich via holes 60 and conductor circuit 58 are arranged are formed onthe both surfaces of the core substrate 30, respectively. Through holes36 are formed in the core substrate 30. Solder resist layers 70 areformed on the upper layers of the respective interlayer resin insulatinglayers 50 and bumps 76U and 76D are formed on the via holes 160 and theconductor circuits 158 through the opening portions 71 of the solderresist layers 70, respectively.

As shown in FIG. 23, solder bumps 76U on the upper surface of themultilayer printed wiring board 10 are connected to lands 92 of the ICchip 90. Further, chip capacitors 98 are mounted on the board 10. On theother hand, conductive connection pins 99 for the connection of the coresubstrate 30 to lower solder bumps are attached to the core substrate30.

The conductor layer 34E is formed to have a thickness of 30 μm. Sincethe capacitors 20 are included in the core substrate 30 according toEmbodiment 6, Embodiment 6 can attain more advantages than those ofEmbodiment 1.

Embodiment 6-1

A multilayer printed wiring board is manufactured in the same manner asthat of Embodiment 6 described above with reference to FIG. 22 exceptfor the following respects:

Thickness of the conductor layers of the core substrate: 30 μm;thickness of the power supply layer of the core substrate: 30 μm;thickness of the conductor layer of the interlayer insulating layer: 15μm.

Embodiment 6-2

A multilayer printed wiring board is manufactured in the same manner asthat of Embodiment 6 except for the following respects:

Thickness of the conductor layers of the core substrate: 55 μm;thickness of the power supply layer of the core substrate: 55 μm;thickness of the conductor layer of the interlayer insulating layer: 15μm.

Embodiment 6-3

Thickness of the conductor layers of the core substrate: 75 μm;thickness of the power supply layer of the core substrate: 75 μm;thickness of the conductor layer of the interlayer insulating layer: 15μm.

Embodiment 6-1

A multilayer printed wiring board is manufactured in the same manner asthat of Embodiment 6-1 except for the following respects:

Thickness of the conductor layers (power supply layer) of the coresubstrate: 180 μm; thickness of the conductor layer of the interlayerinsulating layer: 6.0 μm.

COMPARISON EXAMPLE

In a comparison example for Embodiments 1 to 5, the thickness of thepower supply layer of the core substrate and that of the conductor layerof the interlayer insulating layer are set to satisfy (thickness ofpower supply layer of core substrate/thickness of conductor layer ofinterlayer insulating layer)≦1. As an actual example of the comparisonexample, the thickness of the power supply layer of the core substrateis set at 15 μm and that of the conductor layer of the interlayerinsulating layer is set at 15 μm.

REFERENCE EXAMPLE

In a reference example for Embodiments 1 to 5, the thickness of thepower supply layer of the core substrate and that of the conductor layerof the interlayer insulating layer are set to satisfy (thickness ofpower supply layer of core substrate/thickness of conductor layer ofinterlayer insulating layer)≦40. As an actual example of the referenceexample, the thickness of the power supply layer of the core substrateis set at 415 μm and that of the conductor layer of the interlayerinsulating layer is set at 10 μm.

The reference example means an example which can attain the sameadvantages as those of the appropriate examples; however, to whichdefects may possibly occur and which slightly inappropriate as comparedwith the appropriate examples.

IC chips with a frequency of 3.1 GHz are mounted on the substrateaccording to the embodiments, the comparison example and the referenceexamples, respectively, power equal in quantity is supplied to therespective chips, the voltage drop quantities of the power supplied tothe respective IC chips when the chips are actuated are measured. Theaverages of the voltage drop quantities are shown. The averages arethose of the voltage drop quantities varied at a power supply voltage of1.0 V.

In addition, reliability tests are conducted to the embodiments,comparison example and reference example, respectively, under bias hightemperature, high humidity conditions (130, humidity of 85 wt % andapplication of 2 V). The tests are conducted for test time of 100 hrs,300 hrs, 500 hrs and 1000 hrs, respectively, to inspect thepresence/absence of IC malfunction and the presence/absence of viaconnection opens in the conductor layers of the core for theembodiments, comparison example and reference example, respectively.Test results are shown on tables of FIGS. 27 and 28.

Further, the thicknesses of the conductor layers are inspected. Asimulation result is shown in FIG. 29 with the horizontal axis set at(ratio of thickness of power supply layer of core/thickness ofinterlayer insulating layer) and the vertical axis set at maximumvoltage drop quantity (V).

The graph is made based on the measurement results of all theembodiments, comparison example and reference example while the otherpoints are made by simulation.

FIGS. 27 and 28 demonstrate that the multilayer printed wiring boardsmanufactured in the appropriate embodiments is less prone to themalfunction of the IC chip and opens. Namely, electrical connection andreliability are ensured according to the embodiments.

In the comparison example, the malfunction of the IC chip occurs, sothat electrical connection involves a disadvantage. In addition, becauseof the thin conductors, the stresses generated under the reliabilitytests cannot be buffered and cracks occur to the via connectionportions. As a result, reliability is deteriorated. However, if theratio of the thickness of the power supply layer of the coresubstrate/the thickness of the conductor layer of the interlayerinsulating layer exceeds 1.2, the effect of the thickness ratio appears.

If the ratio of the thickness of the power supply layer of the coresubstrate/the thickness of the conductor layer of the interlayerinsulating layer exceeds 40 (in the reference example), reliability isdeteriorated due to the defects of the upper conductor circuits (e.g.,the generation of stresses to the upper conductor layers, the loweringof adhesion due to waviness and the like). Although no problem normallyoccurs, the tendency appears depending on the factors such as materials.

The test results demonstrate that the thickness of the power supplylayer of the core substrate and that of the conductor layer of theinterlayer insulating layer which satisfy the electrical characteristicsare those which satisfy 1<(thickness of power supply layer of coresubstrate/thickness of conductor layer of interlayer insulating layer).In addition, those which satisfy the factors of the electricalcharacteristics and reliability are those which satisfy (thickness ofpower supply layer of core substrate/thickness of conductor layer ofinterlayer insulating layer)≦40.

The results shown in FIGS. 27 and 28 demonstrate as follows. If thepower supply voltage is 1.0 V and a variation allowable range is ±10%,the behavior of the voltage is stable and the malfunction of the IC chipdoes not occur. Namely, in this case, if the voltage drop quantity iswithin 0.1 V, the malfunction of the IC chip or the like due to thevoltage drop does not occur. If the voltage drop quantity is within 0.09V, reliability improves. For these reasons, it is preferable that theratio of the thickness of the power supply layer of the coresubstrate/the thickness of the conductor layer of the interlayerinsulating layer exceeds 1.2. In addition, if the ratio is1.2=(thickness of power supply layer of core substrate/thickness ofconductor layer of interlayer insulating layer)≦40, the value tends todecrease, so that the advantage can be easily attained. Further, if theratio is 40≦(thickness of power supply layer of core substrate/thicknessof conductor layer of interlayer insulating layer), the voltage dropquantity rises, which follows that a problem occurs to voltage supplydue to the via separation at the core portion or the like. If the viaseparation is suppressed by selecting materials or the like, the problemcan be solved. The problem is not serious in an ordinary range.

Furthermore, if the ratio is 5.0<(thickness of power supply layer ofcore substrate/thickness of conductor layer of interlayer insulatinglayer)≦40, the voltage drop quantities are almost the same and voltagebehavior is, therefore, stable. In other words, this range is the mostpreferable ratio range.

According to this invention, it is possible to decrease the resistancesof the conductors of the IC chip, the substrate and the power supply andthereby decrease transmission loss. Due to this, a signal and power tobe transmitted exhibit desired capabilities. Accordingly, the IC chipnormally functions and operates and no malfunction or error occurs tothe IC chip. It is possible to decrease the resistances of theconductors of the IC chip, the substrate and the earth, decrease thesuperposition of noise on the signal line and power supply line andprevent malfunction or error.

Moreover, it becomes clear that it is possible to decrease the degree ofpower shortage (voltage drop) which occurs at the initial startup of theIC chip according to this invention and that even if an IC chip in ahigh frequency range, particularly an IC chip with 3 GHz or higher, theIC chip can be started without causing any problems. It is therebypossible to improve the electrical characteristics and electricalconnection characteristics.

Additionally, the resistances in the circuits of the printed wiringboard can be decreased as compared with those of the conventionalprinted wiring board. Due to this, even if a reliability test with theapplication of a bias under high temperature, high humidity conditions(high temperature, high humidity bias test) is conducted, destructiontime is lengthened, making it possible to also improve reliability.

1. A multilayer printed wiring board comprising: an interlayer insulating layer and a conductor layer formed on a core substrate, the conductor layer being electrically connected through a via hole, wherein a thickness of the conductor layer on said core substrate is larger than a thickness of the conductor layer on the interlayer insulating layer.
 2. A multilayer printed wiring board comprising: an interlayer insulating layer and a conductor layer formed on a core substrate, the conductor layer being electrically connected through a via hole, wherein if a thickness of the conductor layer on said core substrate is α1 and a thickness of the conductor layer on the interlayer insulating layer is α2, α1 and α2 satisfy α2<α1≦40α2.
 3. The multilayer printed wiring board according to claim 1, wherein said α1 satisfies 2α2≦α1≦40α2.
 4. The multilayer printed wiring board according to claim 1, wherein the conductor layer of said core substrate is the conductor layer for a power supply layer or the conductor layer for an earth.
 5. The multilayer printed wiring board according to claim 1, wherein a capacitor is mounted on a surface of the multilayer printed wiring board.
 6. A multilayer printed wiring board comprising: an interlayer insulating layer and a conductor layer formed on a core substrate, the conductor layer being electrically connected through a via hole, wherein said core substrate is a multilayer core substrate comprising not less than three layers including a thick conductor layer as an inner layer; and the conductor layer as the inner layer and the conductor layer on a surface of said core substrate are the conductor layers for a power supply layer or the conductor layers for an earth.
 7. A multilayer printed wiring board comprising: an interlayer insulating layer and a conductor layer formed on a core substrate, the conductor layer being electrically connected through a via hole, wherein said core substrate is a multilayer core substrate comprising not less than three layers including a thick conductor layer as an inner layer; and a conductor layer as an inner layer of said core substrate is the conductor layer as a power supply layer or the conductor layer as an earth and that a conductor layer on a surface layer of said core substrate comprises a signal line.
 8. A multilayer printed wiring board according to claim 6, wherein a thickness of the conductor layer on said core substrate is larger than a thickness of the conductor layer on the interlayer insulating layer.
 9. The multilayer printed wiring board according to claim 6, wherein the conductor layer as the inner layer of said core substrate is not less than two conductor layers.
 10. The multilayer printed wiring board according to claim 6, wherein said core substrate is constituted so that the conductor layer as said inner layer is formed on each surface of an electrically isolated metallic plate through a resin layer and so that said conductor layer on the surface layer is formed outside of the conductor layer as the inner layer through the resin layer.
 11. The multilayer printed wiring board according to claim 6, wherein said core substrate comprises a thick conductor layer as the inner layer and a thin conductor layer as the conductor layer on the surface layer.
 12. The multilayer printed wiring board according to claim 2, wherein the conductor layer of said core substrate is the conductor layer for a power supply layer or the conductor layer for an earth.
 13. The multilayer printed wiring board according to claim 2, wherein a capacitor is mounted on a surface of the multilayer printed wiring board.
 14. A multilayer printed wiring board according to claim 7, wherein a thickness of the conductor layer on said core substrate is larger than a thickness of the conductor layer on the interlayer insulating layer.
 15. The multilayer printed wiring board according to claim 7, wherein the conductor layer as the inner layer of said core substrate is not less than two conductor layers.
 16. The multilayer printed wiring board according to claim 7, wherein said core substrate is constituted so that the conductor layer as said inner layer is formed on each surface of an electrically isolated metallic plate through a resin layer and so that said conductor layer on the surface layer is formed outside of the conductor layer as the inner layer through the resin layer.
 17. The multilayer printed wiring board according to claim 7, wherein said core substrate comprises a thick conductor layer as the inner layer and a thin conductor layer as the conductor layer on the surface layer. 